现代VLSI电路设计：芯片系统设计 影印本【2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载】

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1 Digital Systems and VLSI1

1.1 Why Design Integrated Circuits?1

1.2 Integrated Circuit Manufacturing4

1.2.1 Technology4

1.2.2 Economics6

1.3 CMOS Technology15

1.3.1 CMOS Circuit Techniques15

1.3.2 Power Consumption16

1.3.3 Design and Testability17

1.4 Integrated Circuit Design Techniques18

1.4.1 Hierarchical Design19

1.4.2 Design Abstraction22

1.4.3 Computer-Aided Design28

1.5 A Look into the Future30

1.6 Summary31

1.7 References31

1.8 Problems32

2 Transistors and Layout33

2.1 Introduction33

2.2 Fabrication Processes34

2.2.1 Overview34

2.2.2 Fabrication Steps37

2.3 Transistors40

2.3.1 Structure of the Transistor40

2.3.2 A Simple Transistor Model45

2.3.3 Transistor Parasitics48

2.3.4 Tub Ties and Latchup50

2.3.5 Advanced Transistor Characteristics53

2.3.6 Leakage and Subthreshold Currents60

2.3.7 Advanced Transistor Structures61

2.3.8 Spice Models61

2.4 Wires and Vias62

2.4.1 Wire Parasitics65

2.4.2 Skin Effect in Copper Interconnect72

2.5 Design Rules74

2.5.1 Fabrication Errors75

2.5.2 Scalable Design Rules77

2.5.3 SCMOS Design Rules79

2.5.4 Typical Process Parameters83

2.6 Layout Design and Tools83

2.6.1 Layouts for Circuits83

2.6.2 Stick Diagrams88

2.6.3 Hierarchical Stick Diagrams90

2.6.4 Layout Design and Analysis Tools95

2.6.5 Automatic Layout99

2.7 References102

2.8 Problems102

3 Logic Gates111

3.1 Introduction111

3.2 Combinational Logic Functions112

3.3 Static Complementary Gates114

3.3.1 Gate Structures115

3.3.2 Basic Gate Layouts118

3.3.3 Logic Levels121

3.3.4 Delay and Transition Time126

3.3.5 Power Consumption135

3.3.6 The Speed-Power Product138

3.3.7 Layout and Parasitics139

3.3.8 Driving Large Loads142

3.4 Switch Logic143

3.5 Alternative Gate Circuits144

3.5.1 Pseudo-nMOS Logic145

3.5.2 DCVS Logic147

3.5.3 Domino Logic149

3.6 Low-Power Gates154

3.7 Delay Through Resistive Interconnect160

3.7.1 Delay Through an RC Transmission Line160

3.7.2 Delay Through RC Trees163

3.7.3 Buffer Insertion in RC Transmission Lines167

3.7.4 Crosstalk Between RC Wires169

3.8 Delay Through Inductive Interconnect172

3.8.1 RLC Basics173

3.8.2 RLC Transmission Line Delay174

3.8.3 Buffer Insertion in RLC Transmission Lines175

3.9 References177

3.10 Problems179

4 Combinational Logic Networks185

4.1 Introduction185

4.2 Standard Cell-Based Layout186

4.2.1 Single-Row Layout Design187

4.2.2 Standard Cell Layout Design196

4.3 Simulation198

4.4 Combinational Network Delay202

4.4.1 Fanout203

4.4.2 Path Delay204

4.4.3 Transistor Sizing209

4.4.4 Automated Logic Optimization218

4.5 Logic and Interconnect Design219

4.5.1 Delay Modeling220

4.5.2 Wire Sizing221

4.5.3 Buffer Insertion222

4.5.4 Crosstalk Minimization224

4.6 Power Optimization229

4.6.1 Power Analysis229

4.7 Switch Logic Networks233

4.8 Combinational Logic Testing237

4.8.1 Gate Testing239

4.8.2 Combinational Network Testing242

4.9 References244

4.10 Problems244

5 Sequential Machines249

5.1 Introduction249

5.2 Latches and Flip-Flops250

5.2.1 Categories of Memory Elements250

5.2.2 Latches252

5.2.3 Flip-Flops259

5.3 Sequential Systems and Clocking Disciplines260

5.3.1 One-Phase Systems for Flip-Flops263

5.3.2 Two-Phase Systems for Latches265

5.3.3 Advanced Clocking Analysis273

5.3.4 Clock Generation280

5.4.1 Structural Specification of Sequential Machines281

5.4 Sequential System Design281

5.4.2 State Transition Graphs and Tables283

5.4.3 State Assignment292

5.5 Power Optimization298

5.6 Design Validation299

5.7 Sequential Testing301

5.8 References308

5.9 Problems308

6 Subsystem Design311

6.1 Introduction311

6.2 Subsystem Design Principles314

6.2.1 Pipelining314

6.2.2 Data Paths316

6.3 Combinational Shifters319

6.4 Adders322

6.5 ALUs329

6.6 Multipliers330

6.7 High-Density Memory339

6.7.1 ROM341

6.7.2 Static RAM343

6.7.3 The Three-Transistor Dynamic RAM347

6.7.4 The One-Transistor Dynamic RAM348

6.8 Field-Programmable Gate Arrays351

6.9 Programmable Logic Arrays352

6.10 References356

6.11 Problems356

7 Floorplanning359

7.1 Introduction359

7.2 Floorplanning Methods360

7.2.1 Block Placement and Channel Definition364

7.2.2 Global Routing370

7.2.3 Switchbox Routing372

7.2.4 Power Distribution373

7.2.5 Clock Distribution376

7.2.6 Floorplanning Tips381

7.2.7 Design Validation382

7.3 Off-Chip Connections383

7.3.1 Packages383

7.3.2 The I/O Architecture387

7.3.3 Pad Design388

7.4 References391

7.5 Problems393

8.1 Introduction399

8 Architecture Design399

8.2 Hardware Description Languages400

8.2.1 Modeling with Hardware Description Languages400

8.2.2 VHDL405

8.2.3 Verilog414

8.2.4 C as a Hardware Description Language421

8.3 Register-Transfer Design422

8.3.1 Data Path-Controller Architectures424

8.3.2 ASM Chart Design425

8.4 High-Level Synthesis434

8.4.1 Functional Modeling Programs436

8.4.2 Data437

8.4.3 Control447

8.4.4 Data and Control453

8.4.5 Design Methodology455

8.5 Architectures for Low Power456

8.5.1 Architecture-Driven Voltage Scaling457

8.5.2 Power-Down Modes458

8.6 Systems-on-Chips and Embedded CPUs459

8.7 Architecture Testing465

8.8 References469

8.9 Problems469

9 Chip Design473

9.1 Introduction473

9.2 Design Methodologies473

9.3 Kitchen Timer Chip482

9.3.1 Timer Specification and Architecture483

9.3.2 Architecture Design485

9.3.3 Logic and Layout Design490

9.3.4 Design Validation497

9.4 Microprocessor Data Path500

9.4.1 Data Path Organization501

9.4.2 Clocking and Bus Design502

9.4.3 Logic and Layout Design504

9.5 References506

9.6 Problems507

10 CAD Systems and Algorithms509

10.1 Introduction510

10.2 CAD Systems510

10.3 Switch-Level Simulation511

10.4 Layout Synthesis513

10.4.1 Placement515

10.4.2 Global Routing518

10.4.3 Detailed Routing520

10.5 Layout Analysis522

10.6 Timing Analysis and Optimization524

10.7 Logic Synthesis529

10.7.1 Technology-Independent Logic Optimization530

10.7.2 Technology-Dependent Logic Optimizations537

10.8 Test Generation540

10.9 Sequential Machine Optimizations542

10.10 Scheduling and Binding544

10.11 Hardware/Software Co-Design546

10.12 References547

10.13 Problems547

A Chip Designer's Lexicon553

B Chip Design Projects571

B.1 Class Project Ideas571

B.2 Project Proposal and Specification572

B.3 Design Plan573

B.4 Design Checkpoints and Documentation576

B.4.1 Subsystems Check577

B.4.2 First Layout Check577

B.4.3 Project Completion577

C Kitchen Timer Model579

C.1 Hardware Modeling in C579

C.1.1 Simulator581

C.1.2 Sample Execution587

Index607